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M93C86, M93C76, M93C66 M93C56, M93C46
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE(R) Serial Access EEPROM
FEATURES SUMMARY

Industry Standard MICROWIRE Bus Single Supply Voltage: - 4.5 to 5.5V for M93Cx6 - 2.5 to 5.5V for M93Cx6-W - 1.8 to 5.5V for M93Cx6-R Dual Organization: by Word (x16) or Byte (x8) Programming Instructions that work on: Byte, Word or Entire Memory Self-timed Programming Cycle with AutoErase: 5ms Ready/Busy Signal During Programming 2MHz Clock Rate Sequential Read Operation Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention Packages - ECOPACK(R) (RoHS compliant)
Figure 1. Packages
8 1
PDIP8 (BN)
8 1
SO8 (MN) 150 mil width
Table 1. Product List
Reference Part Number M93C86 M93C86 M93C86-W M93C86-R M93C76 M93C76 M93C76-W M93C76-R M93C66 M93C66 M93C66-W M93C66-R UFDFPN8 (MB) 2x3mm (MLP) M93C46 M93C56 Reference Part Number M93C56 M93C56-W M93C56-R M93C46 M93C46-W M93C46-R TSSOP8 (DS) 3x3mm body size (MSOP) TSSOP8 (DW) 169 mil width
October 2005
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TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Figure 1. Figure 2. Table 2. Table 3. Table 4. Figure 3. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 INTERNAL DEVICE RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ACTIVE POWER AND STANDBY POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Instruction Set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 6. Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 7. Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Erase/Write Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. READ, WRITE, EWEN, EWDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. ERASE, ERAL Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. WRAL Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10. Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 11. Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Table 12. AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 15. DC Characteristics (M93Cx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 17. DC Characteristics (M93Cx6-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 19. DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 21. AC Characteristics (M93Cx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 23. AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 12.PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 24 Table 24. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 24 Figure 13.SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 25 Table 25. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Data . . . . . . 25 Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15.TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 27. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16.TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 28 Table 28. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 28 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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SUMMARY DESCRIPTION
These electrically erasable programmable memory (EEPROM) devices are accessed through a Serial Data Input (D) and Serial Data Output (Q) using the MICROWIRE bus protocol. In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. Logic Diagram
lect (ORG). The bit, byte and word sizes of the memories are as shown in Table 3. Table 3. Memory Size versus Organization
Device Number of Bits 16384 8192 4096 2048 1024 Number of 8-bit Bytes 2048 1024 512 256 128 Number of 16-bit Words 1024 512 256 128 64
M93C86 M93C76 M93C66 M93C56 M93C46
VCC
The M93Cx6 is accessed by a set of instructions, as summarized in Table 4., and in more detail in Table 5. to Table 7.).
Q
D C M93Cx6 S ORG
Table 4. Instruction Set for the M93Cx6
Instruction READ WRITE EWEN EWDS Description Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data Byte or Word Data Byte or Word Byte or Word
VSS
AI01928
ERASE ERAL WRAL
Table 2. Signal Names
S D Q C ORG VCC VSS Chip Select Input Serial Data Input Serial Data Output Serial Clock Organisation Select Supply Voltage Ground
The memory array organization may be divided into either bytes (x8) or words (x16) which may be selected by a signal applied on Organization Se-
A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially. The address register is automatically incremented after the data is output and, if Chip Select Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the M93C86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6. After the start of the programming cycle, a Busy/Ready signal is available on Serial
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Data Output (Q) when Chip Select Input (S) is driven High. An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when the supply is too low. Figure 3. DIP, SO, TSSOP and MLP Connections (Top View) The DU (Don't Use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or VSS. Direct connection of DU to VSS is recommended for the lowest stand-by power consumption.
M93Cx6 S C D Q 1 2 3 4 8 7 6 5
AI01929B
VCC DU ORG VSS
Note: 1. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1. 2. DU = Don't Use.
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MEMORY ORGANIZATION
The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is selected. When the M93Cx6 is in stand-by mode, Organization Select (ORG) should be set either to VSS or VCC for minimum power consumption. Any voltage between VSS and VCC applied to Organization Select (ORG) may increase the stand-by current.
INTERNAL DEVICE RESET
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up and Power-down, the device must not be selected (that is, the Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating voltage VCC (as defined in Tables 9, 10 and 11). During Power-up (phase during which VCC is lower than VCCmin but increases continuously), the device will not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in DC AND AC PARAMETERS). Once VCC has passed the POR threshold, the device is reset. Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). During Power-down (phase during which VCC decreases continuously), as soon as VCC drops from the normal operating voltage below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it.
ACTIVE POWER AND STANDBY POWER MODES
When Chip Select (S) is High, the device is selected and in the Active Power mode. It consumes ICC, as specified in Tables 15, 16, 17, 18 and 19. When Chip Select (S) is Low, the device is deselected. If no Erase/Write cycle is in progress when Chip Select goes Low, the device enters the Standby Power mode, and the power consumption drops to ICC1. For the M93Cx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Cx6W (3V range) and M93Cx6-R (2V range) the POR threshold voltage is around 1.5V.
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INSTRUCTIONS
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in Table 5. to Table 7.. Each instruction consists of the following parts, as shown in Figure 4.: Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low. A start bit, which is the first `1' read on Serial Data Input (D) during the rising edge of Serial Clock (C). Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). Table 5. Instruction Set for the M93C46
x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address(1) Data Required Clock Cycles x16 Origination (ORG = 1) Address(1) Data Required Clock Cycles
The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 5.). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 6.). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 7.). The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 20. to Table 23..
READ WRITE EWEN EWDS ERASE ERAL WRAL
Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
1 1 1 1 1 1 1
10 01 00 00 11 00 00
A6-A0 A6-A0 11X XXXX 00X XXXX A6-A0 10X XXXX 01X XXXX
Q7-Q0 D7-D0 18 10 10 10 10 D7-D0 18
A5-A0 A5-A0 11 XXXX 00 XXXX A5-A0 10 XXXX 01 XXXX
Q15-Q0 D15-D0 25 9 9 9 9 D15-D0 25
Note: 1. X = Don't Care bit.
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Table 6. Instruction Set for the M93C56 and M93C66
x8 Origination (ORG = 0) Instruction Description Start bit OpCode Address(1,2) Data x16 Origination (ORG = 1) Data Required Clock Cycles Required Clock Address(1,3) Cycles A7-A0 20 12 12 12 12 D7-D0 20 A7-A0 11XX XXXX 00XX XXXX A7-A0 10XX XXXX 01XX XXXX D15-D0
READ WRITE EWEN EWDS ERASE ERAL WRAL
Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
1 1 1 1 1 1 1
10 01 00 00 11 00 00
A8-A0 A8-A0 1 1XXX XXXX 0 0XXX XXXX A8-A0 1 0XXX XXXX 0 1XXX XXXX
Q7-Q0 D7-D0
Q15-Q0 D15-D0 27 11 11 11 11 27
Note: 1. X = Don't Care bit. 2. Address bit A8 is not decoded by the M93C56. 3. Address bit A7 is not decoded by the M93C56.
Table 7. Instruction Set for the M93C76 and M93C86
x8 Origination (ORG = 0) Instruction Description Start bit OpCode Address(1,2) Data x16 Origination (ORG = 1) Data Required Clock Cycles Required Clock Address(1,3) Cycles A9-A0 22 14 14 14 14 D7-D0 22 A9-A0 11 XXXX XXXX 00 XXXX XXXX A9-A0 10 XXXX XXXX 01 XXXX XXXX D15-D0
READ WRITE EWEN EWDS ERASE ERAL WRAL
Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
1 1 1 1 1 1 1
10 01 00 00 11 00 00
A10-A0 A10-A0 11X XXXX XXXX 00X XXXX XXXX A10-A0 10X XXXX XXXX 01X XXXX XXXX
Q7-Q0 D7-D0
Q15-Q0 D15-D0 29 13 13 13 13 29
Note: 1. X = Don't Care bit. 2. Address bit A10 is not decoded by the M93C76. 3. Address bit A9 is not decoded by the M93C76.
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Read The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or 16bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. Erase/Write Enable and Disable The Erase/Write Enable (EWEN) instruction enables the future execution of erase or write instructions, and the Erase/Write Disable (EWDS) instruction disables it. When power is first applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Erase/Write Enable (EWEN) instruction has been executed, erasing and writing remains enabled until an Erase/ Write Disable (EWDS) instruction is executed, or until VCC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Erase/Write Disable (EWDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Erase/ Write Enable (EWEN) or Erase/Write Disable (EWDS) instructions.
Figure 4. READ, WRITE, EWEN, EWDS Sequences
READ S
D
1 1 0 An
A0
Q ADDR OP CODE
Qn DATA OUT
Q0
WRITE
S CHECK STATUS D 1 0 1 An A0 Dn D0
Q ADDR OP CODE DATA IN BUSY READY
ERASE WRITE ENABLE
S
ERASE WRITE DISABLE 1 0 0 1 1 Xn X0
S
D
D
1 0 0 0 0 Xn X0
OP CODE
Note: For the meanings of An, Xn, Qn and Dn, see Table 5., Table 6. and Table 7..
OP CODE
AI00878C
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Erase The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the Ready/ Busy line, as described in the READY/BUSY STATUS section. Write For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be written. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C). Figure 5. ERASE, ERAL Sequences
ERASE S CHECK STATUS D 1 1 1 An A0
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be detected by monitoring the Ready/Busy line, as described later in this document. Once the Write cycle has been started, it is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction.
Q ADDR OP CODE BUSY READY
ERASE ALL
S CHECK STATUS D 1 0 0 1 0 Xn X0
Q ADDR OP CODE
AI00879B
BUSY
READY
Note: For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..
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Erase All The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1). The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be detected by monitoring the Ready/Busy line, as described in the READY/BUSY STATUS section. Write All As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy address be provided. As with the Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. This value is written to all the addresses of the memory device. The completion of the cycle can be detected by monitoring the Ready/Busy line, as described next.
Figure 6. WRAL Sequence
WRITE ALL S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0
Q ADDR OP CODE
AI00880C
DATA IN
BUSY
READY
Note: For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..
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READY/BUSY STATUS
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select Input (S) is driven High. (Please note, though, that there is an initial delay, of tSLSH, before this status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Select Input (S) is driven High, the Ready signal (Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought Low or until a new start bit is decoded.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). may lead to the writing of erroneous data at an erroneous address. To combat this problem, the M93Cx6 has an onchip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Cx6 family, are summarized in Table 5. to Table 7.. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 9 Address bits + 8 Data bits
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details.
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 7.) and Figure 7. Write Sequence with One Clock Glitch
S
C
D
An START "0" WRITE "1"
An-1 Glitch
An-2 D0
ADDRESS AND DATA ARE SHIFTED BY ONE BIT
AI01395
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M93C86, M93C76, M93C66, M93C56, M93C46
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 8. Absolute Maximum Ratings
Symbol TA TSTG TLEAD VOUT VIN VCC VESD Parameter Ambient Operating Temperature Storage Temperature PDIP-Specific Lead Temperature during Soldering Output range (Q = VOH or Hi-Z) Input range Supply Voltage Electrostatic Discharge Voltage (Human Body model)(2) -0.50 -0.50 -0.50 -4000 Min. -40 -65 Max. 130 150 260(1) VCC+0.5 VCC+1 6.5 4000 Unit C C C V V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. TLEADmax must not be applied for more than 10s. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ).
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DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 9. Operating Conditions (M93Cx6)
Symbol VCC Supply Voltage Ambient Operating Temperature (Device Grade 6) TA Ambient Operating Temperature (Device Grade 7) Ambient Operating Temperature (Device Grade 3) Parameter Min. 4.5 -40 -40 -40 Max. 5.5 85 105 125 Unit V C C C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 10. Operating Conditions (M93Cx6-W)
Symbol VCC Supply Voltage Ambient Operating Temperature (Device Grade 6) TA Ambient Operating Temperature (Device Grade 7) Ambient Operating Temperature (Device Grade 3) Parameter Min. 2.5 -40 -40 -40 Max. 5.5 85 105 125 Unit V C C C
Table 11. Operating Conditions (M93Cx6-R)
Symbol VCC TA Supply Voltage Ambient Operating Temperature (Device Grade 6) Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C
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Table 12. AC Measurement Conditions (M93Cx6)
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.4 V to 2.4 V 1.0 V and 2.0 V 0.8 V and 2.0 V
ns V V V
Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC 0.3VCC to 0.7VCC
ns V V V
Figure 8. AC Testing Input Output Waveforms
M93CXX 2.4V 2V 1V 0.4V INPUT OUTPUT 2.0V 0.8V
M93CXX-W & M93CXX-R 0.8VCC 0.7VCC 0.3VCC
AI02553
0.2VCC
Table 14. Capacitance
Symbol COUT CIN Parameter Output Capacitance Input Capacitance Test Condition VOUT = 0V VIN = 0V Min Max 5 5 Unit pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 1MHz.
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Table 15. DC Characteristics (M93Cx6, Device Grade 6)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz, Q = open VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC VCC = 5V 10% VCC = 5V 10% VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 -0.45 2 Min. Max. 2.5 2.5 2 15 0.8 VCC + 1 0.4 Unit A A mA A V V V V
Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz, , Q = open VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC VCC = 5V 10% VCC = 5V 10% VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 -0.45 2 Min. Max. 2.5 2.5 2 15 0.8 VCC + 1 0.4 Unit A A mA A V V V V
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Table 17. DC Characteristics (M93Cx6-W, Device Grade 6)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S) VCC = 5V, IOL = 2.1mA VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100A VCC = 5V, IOH = -400A VOH Output High Voltage (Q) VCC = 2.5V, IOH = -100A VCC-0.2 V 2.4 0.2 V V Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz, Q = open VCC = 2.5V, S = VIH, f = 2 MHz, Q = open VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC -0.45 0.7 VCC Min. Max. 2.5 2.5 2 1 5 0.2 VCC VCC + 1 0.4 Unit A A mA mA A V V V
ICC1 VIL VIH
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Table 18. DC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S) VCC = 5V, IOL = 2.1mA VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100A VCC = 5V, IOH = -400A VOH Output High Voltage (Q) VCC = 2.5V, IOH = -100A VCC-0.2 V 2.4 0.2 V V Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz, Q = open VCC = 2.5V, S = VIH, f = 2 MHz, Q = open VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC -0.45 0.7 VCC Min. (1) Max. (1) 2.5 2.5 2 1 5 0.2 VCC VCC + 1 0.4 Unit A A mA mA A V V V
ICC1 VIL VIH
Note: 1. New product: identified by Process Identification letter W or G or S.
Table 19. DC Characteristics (M93Cx6-R)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S) Output Low Voltage (Q) Output High Voltage (Q) VCC = 1.8V, IOL = 100A VCC = 1.8V, IOH = -100A VCC-0.2 Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz, Q = open VCC = 1.8V, S = VIH, f = 1 MHz, Q = open VCC = 1.8V, S = VSS, C = VSS, ORG = VSS or VCC -0.45 0.8 VCC Min. (1) Max. (1) 2.5 2.5 2 1 2 0.2 VCC VCC + 1 0.2 Unit A A mA mA A V V V V
ICC1 VIL VIH VOL VOH
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
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M93C86, M93C76, M93C66, M93C56, M93C46
Table 20. AC Characteristics (M93Cx6, Device Grade 6, 7 or 3)
Test conditions specified in Table 12. and Table 9. Symbol fC tSLCH Alt. fSK Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time M93C46, M93C56, M93C66 tSHCH tCSS Chip Select Set-up time M93C76, M93C86 Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min. D.C. 50 50 50 200 200 200 50 50 50 0 200 100 200 200 5 Max. 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tSLSH(2) tCHCL(1) tCLCH(1) tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW
tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
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Table 21. AC Characteristics (M93Cx6-W, Device Grade 6)
Test conditions specified in Table 13. and Table 10. Symbol fC tSLCH tSHCH tSLSH(2) tCHCL(1) tCLCH(1) tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min. D.C. 50 50 200 200 200 50 50 50 0 200 100 200 200 5 Max. 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
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Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Test conditions specified in Table 13. and Table 10. Symbol fC tSLCH tSHCH tSLSH(2) tCHCL(1) tCLCH(1) tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min. D.C. 50 50 200 200 200 50 50 50 0 200 100 200 200 5 Max. 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
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Table 23. AC Characteristics (M93Cx6-R)
Test conditions specified in Table 13. and Table 11. Symbol fC tSLCH tSHCH tSLSH(2) tCHCL(1) tCLCH(1) tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min.(3) D.C. 250 50 250 250 250 100 100 100 0 400 200 400 400 10 Max.(3) 1 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. This product is under development. For more information, please contact your nearest ST sales office.
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Figure 9. Synchronous Timing (Start and Op-Code Input)
tCLSH C tSHCH S tDVCH D START OP CODE OP CODE tCHDX tCLCH tCHCL
START
OP CODE INPUT
AI01428
Figure 10. Synchronous Timing (Read or Write)
C tCLSL S tDVCH D An tCHQL Q15/Q7 tCHDX A0 tSLQZ Q0 tCHQV tSLSH
Hi-Z Q
ADDRESS INPUT
DATA OUTPUT
AI00820C
Figure 11. Synchronous Timing (Read or Write)
tSLCH C tCLSL S tDVCH D An tCHDX A0/D0 tSHQV Hi-Z Q BUSY tW ADDRESS/DATA INPUT WRITE CYCLE
AI01429
tSLSH
tSLQZ READY
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M93C86, M93C76, M93C66, M93C56, M93C46
PACKAGE MECHANICAL
Figure 12. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Note: Drawing is not to scale.
Table 24. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
millimeters Symbol Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
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Figure 13. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A2 B e D A C ddd
8
E
1
H A1 L
SO-A
Note: Drawing is not to scale.
Table 25. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Data
millimeters Symbol Typ A A1 A2 B C D ddd E e H h L N (pin number) 1.27 3.80 - 5.80 0.25 0.40 0 8 Min 1.35 0.10 1.10 0.33 0.19 4.80 Max 1.75 0.25 1.65 0.51 0.25 5.00 0.10 4.00 - 6.20 0.50 0.90 8 0.050 0.150 - 0.228 0.010 0.016 0 8 Typ Min 0.053 0.004 0.043 0.013 0.007 0.189 Max 0.069 0.010 0.065 0.020 0.010 0.197 0.004 0.157 - 0.244 0.020 0.035 8 inches
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M93C86, M93C76, M93C66, M93C56, M93C46
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Outline
D L3
e
b L1
E
E2
L A D2 ddd A1
UFDFPN-01
Note: 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Data
millimeters Symbol Typ. A A1 b D D2 ddd E E2 e L L1 L3 N (pin number) 0.30 8 0.50 0.45 3.00 0.15 - 0.40 0.25 - 0.50 0.15 0.012 8 0.020 0.018 0.25 2.00 1.55 1.65 0.05 0.118 0.006 - 0.016 0.010 - 0.020 0.006 0.55 Min. 0.50 0.00 0.20 Max. 0.60 0.05 0.30 0.010 0.079 0.061 0.065 0.002 Typ. 0.022 Min. 0.020 0.000 0.008 Max. 0.024 0.002 0.012 inches
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Figure 15. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline
D
8
5 E1 E
c
1
4
A1 A CP b e A2
L L1
TSSOP8BM
Note: Drawing is not to scale.
Table 27. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
millimeters Symbol Typ. A A1 A2 b c D E E1 e CP L L1 N (pin number) 0.550 0.950 0 8 6 0.400 3.000 4.900 3.000 0.650 0.850 0.050 0.750 0.250 0.130 2.900 4.650 2.900 - Min. Max. 1.100 0.150 0.950 0.400 0.230 3.100 5.150 3.100 - 0.100 0.700 0.0217 0.0374 0 8 6 0.0157 0.1181 0.1929 0.1181 0.0256 0.0335 0.0020 0.0295 0.0098 0.0051 0.1142 0.1831 0.1142 - Typ. Min. Max. 0.0433 0.0059 0.0374 0.0157 0.0091 0.1220 0.2028 0.1220 - 0.0039 0.0276 inches
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Figure 16. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Note: Drawing is not to scale.
Table 28. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
millimeters Symbol Typ. A A1 A2 b c CP D e E E1 L L1 N (pin number) 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
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PART NUMBERING
Table 29. Ordering Information Scheme
Example: Device Type M93 = MICROWIRE serial access EEPROM Device Function 86 = 16 Kbit (2048 x 8) 76 = 8 Kbit (1024 x 8) 66 = 4 Kbit (512 x 8) 56 = 2 Kbit (256 x 8) 46 = 1 Kbit (128 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) MB = UDFDFPN8 (MLP8) DW = TSSOP8 (169 mil width) DS = TSSOP8 (3x3mm body size) Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 7 = Device tested with High Reliability Certified Flow(1). Automotive temperature range (-40 to 105 C) 3 = Device tested with High Reliability Certified Flow(1). Automotive temperature range (-40 to 125 C) Packing blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK(R) (RoHS compliant) Process(2) /W or /S = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for Device Grade 3.
M93C86
-
W MN 6
T
P
/S
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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REVISION HISTORY
Table 30. Document Revision History
Date Rev. Description of Revision Document reformatted, and reworded, using the new template. Temperature range 1 removed. TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added, with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and corresponding parameters adjusted) Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges VOUT and VIN separated from VIO in the Absolute Maximum Ratings table Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices with Process Identification Letter W Standby current corrected for -R range Turned-die option re-instated in Ordering Information Scheme Table of contents, and Pb-free options added. Temperature range 7 added. VIL(min) improved to -0.45V. MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified. Process identification letter "G" information added M93C06 removed. Device grade information further clarified. Process identification letter "S" information added. Turned-die package option removed. Product list summary added. current product/new product distinction removed. ICC and ICC1 values for current product removed from tables 15, 16 and 17 and AC characteristics for current product removed from Tables 20 and 21. Clock rate added to FEATURES SUMMARY. "Q = open" added to ICC Test conditions in DC Characteristics Tables 15, 16, 17, 18 and 19. 27-Oct-2005 6.0 Process(2) added to Table 29., Ordering Information Scheme. POWER ON DATA PROTECTION section removed, replaced by INTERNAL DEVICE RESET and ACTIVE POWER AND STANDBY POWER MODES. INITIAL DELIVERY STATE added. SO8N and TSSOP8 packages updated. PDIP-specific TLEAD added to Table 8., Absolute Maximum Ratings.
04-Feb-2003
2.0
26-Mar-2003 04-Apr-2003 23-May-2003 27-May-2003 25-Nov-2003
2.1 2.2 2.3 2.4 3.0
30-Mar-2004
4.0
16-Aug-2004
5.0
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M93C86, M93C76, M93C66, M93C56, M93C46
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